History

The roots of this design can be found in a sticky thread at www.diyaudio.com. Somewhere around page 65, a new symmetrical design was published, in an attempt to solve the well known VAS bias instability that usually plagues such a design. The solution was there to add diamond style current sources, defining a constant voltage drop at the input of the emitter follower that isolates the input stage to the VAS. This solution was heavily criticized as being suboptimal, mainly because the input stage voltage gain was limited by the relatively small resistor (load) required to set the VAS bias.

Several improvements were suggested. Edmond published his approach, built around what was eventually defined as Common Mode Current Loop (CMCL) to stabilize the VAS bias (also avoiding the “fighting VAS”, a potential issue in fully symmetrical designs) and a NDFL (also see the references in this article) approach to improve the frequency response of the negative feedback loop over the classic one or two pole compensation.

Ovidiu was lurking around and, after breadboarding the original circuit (with mediocre results, given the project scope), was interested in Edmond’s approach. He breadboarded Edmond’s design, integrated with the already existing Error Correction (EC) based Output Power Stage (OPS) and reported back some issues regarding the thermal stability of the circuit. Which triggered several full redesigns and ultimately to the circuit presented here.

The Class AB EC OPS that Ovidiu developed early in the year was based on Bob Cordell’s design and further optimized for lateral 2SK1058/2SJ162 MOSFETs. The reason to chose lateral MOSFETs was entirely based on their self-protecting nature. It is in our belief that an I/V protection circuit that would not interfere with the AC performance doesn’t currently exist. Therefore, vertical MOSFETs or power bipolar devices would render an amp that is virtually unprotected to accidental (short circuits) or difficult speaker loads. Lateral MOSFETs have the unique property in that their transconductance collapses at high currents, being therefore more tolerant to abuse. The EC OPS board (that required three iterations to optimize) would accommodate, with some component values adjustments, all three types of output devices (lateral MOSFETs, vertical MOSFETs and power BJTs).

A second front end design included an intermediate gain stage (which is natural in a NDFL schema) and a unique approach to compensate for the evil Early voltage: rather than including cascode devices in all stages, the input stage supply voltages were themselves modulated (bootstrapped) by the output voltage.

The third and final design included a high performance modulated power supply, with excellent noise and distortion performance and improved PSRR and line regulation, an original overload protection (integrated with the NDFL) and an improved low noise bias circuit.

The active devices used to build this amp were subject to numerous changes across the lifetime of the project. Originally, the amp was designed and experimented with 2N5551/2N5401 TO92 small signal, 2SD669/2SB649 TO126 medium power and MJ15030/MJ15031 TO220 medium power (drivers in the EC OPS). After the first design experienced severe thermal drift issues, fears of relapsing of such issues led to replacing 2N5551/2N5401 with their dual versions (MMTD5551/MMTD5401) in SOT363. Performance was good, but still far from the desired target. It was then a major decision to switch entirely to japanese BJTs. Under these new circumstances, using 2SC3601/2SA1407 in the differential error amp and 2SC5171/2SA1930 in the drivers, the Class AB EC OPS open loop THD-20 (80KHz bandwidth) went down from 0.022% to a reproducible 0.008%, requiring though 0.1% critical components (a few resistors) tolerances. The front end benefited from the low noise 2SC22240/2SA970 in the input stage and the ultra high performance 2SC3601/2SA1407 in the VAS. The need to keep the front end devices temperature low, without making use of bulky heatsinks, required using a few TO126 devices in the signal path; 2SC3421/2SA1358 pairs were selected.

All circuitry was initially experimented on 3M breadboards. Although it is widely believed that nothing of ultra high performance can be built on breadboards, our experience was entirely positive. Good quality breadboards (as usual, forget those Chinese cheapos!), a careful breadboarding layout and the usual grounding best practices led us to measured performances that justified designing the PCBs. We were able to measure 0.00014% (1.4ppm) THD20 distortion on a breadboarded version of the front end, coupled with the finished Class AB EC OPS!

Click here for a few pictures taken during the development phase.